Electrostatic protection circuits for integrated circuit devices are described, for example, in Patent Document 1 and Patent Document 2. Patent Document 1 describes an electrostatic protection circuit that protects an internal circuit from electrostatic destruction, when an excessive voltage is applied to an input-output pad (a common terminal for signal input and signal output), by circulating a transient current to a power supply line or a ground line via a resistor and a diode.
Also, Patent Document 2 describes an electrostatic protection circuit that composes a voltage tolerance circuit using the so-called floating N well technology. The voltage tolerance circuit does not have any particular definition, but is an input-output interface circuit that uses a circuit composition that does not allow an unnecessary current to flow from an input side to a power supply side when a voltage higher than the power supply voltage VDD of the internal circuit is inputted in an input-output pad or the like, thereby improving the voltage tolerance.
Also, the floating N-well technology is one of the methods for composing a voltage tolerance circuit in which, for example, the potential on an N-well region where a PMOS transistor is formed is not fixed at a high level power supply voltage VDD, and the voltage on the N-well is made adaptively adjustable. By this, when an excessive electrostatic surge or the like exceeding the VDD is applied to the source of the PMOS transistor, a parasitic diode present between its source (P-type impurity region) and the N-well is prevented from turning on, thereby preventing a large transient current from flowing in the power supply line (VDD line) through the parasitic diode, and thereby preemptively preventing malfunction of the circuit and destruction of the elements and wirings.